Title :
Connecting pre-silicon and post-silicon verification
Author :
Ray, Sandip ; Hunt, Warren A., Jr.
Author_Institution :
Dept. of Comput. Sci., Univ. of Texas at Austin, Austin, TX, USA
Abstract :
We present a framework for post-silicon analysis, that provides a formal, bidirectional communication with pre-silicon verification. We show how to exploit the framework to provide a formal guarantee on post-silicon verification accuracy under limited observability. In particular, we partition a pre-silicon assertion checker (with full observability) into (1) a limited-observability checker and (2) an in-silicon integrity unit. The composition of the two units is guaranteed to provide the same accuracy as a pre-silicon checker. We apply the framework in the verification of a cache system.
Keywords :
cache storage; formal logic; formal verification; hardware description languages; cache system verification; in-silicon integrity unit; limited-observability checker; post-silicon verification; pre-silicon assertion checker; pre-silicon verification; Bidirectional control; Costs; Counting circuits; Databases; Hardware design languages; Instruments; Joining processes; Monitoring; Observability; Silicon;
Conference_Titel :
Formal Methods in Computer-Aided Design, 2009. FMCAD 2009
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-4966-8
Electronic_ISBN :
978-1-4244-4966-8
DOI :
10.1109/FMCAD.2009.5351128