DocumentCode
2646875
Title
Scalable conditional equivalence checking: An automated invariant-generation based approach
Author
Baumgartner, Jason ; Mony, Hari ; Case, Michael ; Sawada, Jun ; Yorav, Karen
fYear
2009
fDate
15-18 Nov. 2009
Firstpage
120
Lastpage
127
Abstract
Sequential equivalence checking (SEC) technologies, capable of demonstrating the behavioral equivalence of two designs, have grown dramatically in capacity over the past decades. The ability to efficiently identify and leverage internal equivalence points to reduce the domain of the overall SEC problem is central to SEC scalability. However, conditionally equivalent designs - within which internal equivalence may not exist under sequential observability don´t care conditions - are notoriously difficult for automated SEC tools. This paper constitutes one of the first attempts to advance the scalability of SEC for conditionally equivalent designs through automated invariant generation, which enables an inductive solution to an otherwise highly-noninductive problem. Through careful software engineering and various heuristics, this technique has been demonstrated capable of yielding orders of magnitude speedup on difficult industrial conditional SEC problems, in cases constituting the only method that we have found to achieve an automated solution.
Keywords
clocks; logic design; logic gates; automated SEC tools; automated invariant-generation based approach; clock-gated pipeline; scalable conditional equivalence checking; software engineering; Clocks; Computer industry; Hardware design languages; Laboratories; Merging; Observability; Pipelines; Scalability; Signal design; Software engineering;
fLanguage
English
Publisher
ieee
Conference_Titel
Formal Methods in Computer-Aided Design, 2009. FMCAD 2009
Conference_Location
Austin, TX
Print_ISBN
978-1-4244-4966-8
Electronic_ISBN
978-1-4244-4966-8
Type
conf
DOI
10.1109/FMCAD.2009.5351131
Filename
5351131
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