Study of power module package structures

Author

Ohbu, Toshiharu ; Kodani, Kazuya ; Tada, Nobumitsu ; Matsumoto, Toshiaki ; Kijima, Kenji ; Saito, Suzuo

Author_Institution

Toshiba Corp., Tokyo, Japan

fYear

2000

fDate

2000

Firstpage

46

Lastpage

50

Abstract

In order to realize a high current power module, we studied optimum chip layout with lowest chip temperature rise, and the reduction method of contact thermal resistance. We showed that about 24% reduction of chip temperature rise was possible. In order to inhibit surge voltages, we studied the optimum bus-bar structure. The stray inductance of the bus-bar showed that about 40% reduction was possible

Keywords

busbars; circuit layout; circuit optimisation; heating; inductance; modules; optimisation; power semiconductor devices; semiconductor device packaging; surge protection; thermal management (packaging); thermal resistance; bus-bar stray inductance; chip temperature; chip temperature rise; contact thermal resistance reduction method; high current power module; optimum bus-bar structure; optimum chip layout; power module package structures; surge voltages; Cogeneration; Contact resistance; Copper; Electronic packaging thermal management; Heat sinks; Insulation; Multichip modules; Temperature distribution; Thermal resistance; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Power Packaging, 2000. IWIPP 2000. International Workshop on

Conference_Location

Waltham, MA

Print_ISBN

0-7803-6437-6

Type

conf

DOI

10.1109/IWIPP.2000.885180

Filename

885180