A Novel Efficient VLSI Architecture of 2-D Discrete Wavelet Transform

In this paper, we propose a novel, efficient VLSI architecture for the implementation of the forward two-dimension, lifting-based discrete wavelet transform (DWT). Replacing the conventional rows and columns alternatively separable method, we extend the 1D-DWT into 2D-DWT directly. The architecture was designed based on the results. The proposed architecture can speed up the computation time to N/2* N/2 for the first level decomposition on an N*N image. The architecture is coded in Verilog HDL and verified by the platform of Quartus-II. Finally it is implemented in an Altera Cyclone family FPGA.