Low Power Adders Design for Portable Video Terminal

Many low power CMOS 1-bit full adder cells, formed by transmission gates, have been presented recently. However, the performance of low power adders, directly formed by those 1-bit full adder cells, is not the best. This paper presents a new tapered transmission gate that decreases the propagation delay in the carry chains without increasing power consumption. The design provides an alternative and complementary solution for decreasing the carry propagation delay in low power cell, particularly for those cases where chains of transmission gates are used.