Design of a 2.5Gbps Clock-Data Recovery circuit in 0.18um standard CMOS process

Author

Yueyang, Chen ; Zhong Shun´an ; Hua, Dang

Author_Institution

Sch. of Inf. & Electron., Beijing Inst. of Technol., Beijing, China

fYear

2009

fDate

20-23 Oct. 2009

Firstpage

1153

Lastpage

1156

Abstract

A 2.5 Gbps clock-data recovery (CDR) circuit is designed in 0.18 um standard CMOS process in this work. The CDR circuit utilizes one PLL loop and one CMU loop. The CDR loop works at 2.5 GHz by SONET OC-48 while the CMU loop runs at 625 MHz.The power consumption is 25 mW. The jitter bandwidth is 5.6 MHz. The peaking is 2.67 dB. The VCO gain is 163 MHz/V with a tuning range of 390 MHz. The output data and clock amplitude is 500 mV SEPP (single-ended peak to peak). Random jitter is 0.1 mUI rms and the output data ISI is 10 mUI.

Keywords

CMOS integrated circuits; clock and data recovery circuits; clocks; phase locked loops; synchronisation; voltage-controlled oscillators; CDR circuit; CDR loop; CMU loop; PLL loop; SONET OC-48; VCO gain; bandwidth 5.6 MHz; bit rate 2.5 Gbit/s; clock amplitude; clock data recovery circuit; complementary metal-oxide-semiconductor; frequency 2.5 GHz; frequency 390 MHz; frequency 625 MHz; jitter bandwidth; phase locked loops; power 25 mW; random jitter; single-ended peak to peak; size 0.18 mum; standard CMOS process; voltage 500 mV; voltage-controlled oscillators; Bandwidth; CMOS process; Circuits; Clocks; Energy consumption; Gain; Jitter; Phase locked loops; SONET; Voltage-controlled oscillators; CDR; CMOS; CMU; PLL; high-speed;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Conference_Location

Changsha, Hunan

Print_ISBN

978-1-4244-3868-6

Electronic_ISBN

978-1-4244-3870-9

Type

conf

DOI

10.1109/ASICON.2009.5351164

Filename

5351164