DocumentCode
2647331
Title
Logic simulation with interval-labelled net model
Author
Chiu, Peter P K ; Cheung, Y.S.
Author_Institution
Dept. of Electron. Eng., Hong Kong Polytech., Hung Hom, Hong Kong
fYear
1989
fDate
11-13 Dec 1989
Firstpage
132
Lastpage
141
Abstract
A novel approach to the application of an interval-labeled net model in logic simulation with timing among concurrent processes is introduced. By means of the model, logic circuit properties involving timing information can be specified and simulated in a multiprocessor-based environment using the token-passing algorithm. A logic simulator with timing information with a structure based on this approach is proposed
Keywords
logic CAD; modelling; concurrent processes; interval-labelled net model; logic circuit properties; logic simulation; multiprocessor-based environment; timing; token-passing algorithm; Circuit simulation; Coupling circuits; Discrete event simulation; Flip-flops; Logic circuits; Logic gates; Multiprocessing systems; Pulse inverters; System recovery; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Petri Nets and Performance Models, 1989. PNPM89., Proceedings of the Third International Workshop on
Conference_Location
Kyoto
Type
conf
DOI
10.1109/PNPM.1989.68547
Filename
68547
Link To Document