Title :
TITAC-2: an asynchronous 32-bit microprocessor
Author :
Takamura, Akihiro ; Imai, Masashi ; Ozawa, Motokazu ; Fukasaku, Izumi ; Fujii, Taro ; Kuwako, Masashi ; Ueno, Yoichiro ; Nanya, Takashi
Author_Institution :
Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
Abstract :
With the wire-delay problem moving into dominance in VLSI chip design, a fundamental limitation is being revealed in performance and dependability of synchronous systems which require global clock distribution with as little skew as possible. The worst-case delay is influenced not only by design and fabrication process but also by the operating environment, e.g. the power supply voltage and temperature. Asynchronous systems, with no global clock, can intrinsically enjoy: 1) average case performance instead of worst-case performance, 2) low power consumption, 3) ease of modular design, and 4) timing fault tolerance. We have designed and implemented a 32-bit fully asynchronous microprocessor, TITAC-2, which is the fastest and largest CMOS asynchronous microprocessor that has ever been operational
Keywords :
VLSI; microprocessor chips; performance evaluation; 32 bit; 32-bit microprocessor; CMOS asynchronous microprocessor; TITAC-2; VLSI chip design; performance; wire-delay; Chip scale packaging; Clocks; Delay; Fabrication; Microprocessors; Power supplies; Process design; Temperature; Very large scale integration; Voltage;
Conference_Titel :
Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-4425-1
DOI :
10.1109/ASPDAC.1998.669480