A multi-processing architecture for accelerating Haar-based face detection on FPGA

Obtaining a real-time implementation for a face detection system is the first step towards human-machine interaction. This paper presents an architecture, implementable on an FPGA, for accelerating the Haar-based face detection algorithm through use of multiple dedicated processing units by utilizing the inherent parallelism in the algorithm. The architecture is designed to be scalable and the face detection load has been distributed among the processing units so as to reduce the idle time. The design has been synthesized for the Xilinx Virtex-5 board. Use of a single processing unit gives an improvement in the face detection frame rate of 5.45 times over an Intel i5, 2.4 GHz processor. The frame rate is further doubled by scaling the architecture to include four processing units running in parallel.