Full coverage location of logic resource faults in A SOC co-verification technology based FPGA functional test environment

Full coverage location of logic resource faults is vital for FPGA design and fabrication, rather than only detecting whether there are faults or not. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, SOC co-verification technology based in-house FPGA functional test environment embedded with an in-house computerized tool, ConPlacement, can locate logic resources automatically, exhaustively and repeatedly. The approach to implement full coverage location of configurable logic block (CLB) faults by the FPGA functional test environment is presented in the paper. Experimental results of XC4010E demonstrate that full coverage location of logic resource faults as well as multi-faults position can be realized.