Metal gate stack plasma patterning studies

Summary form only given. The presentation will focus on the dry etch studies required to pattern poly-Si/metal/SiON and poly-Si/metal/high-k gate stacks that might be used in the forthcoming technological nodes. As usual, two key challenges for dry etching metal gate stacks are selectivity and profile control. Smaller and smaller dimensions with more and more complex gate stacks with new materials make those challenges even more difficult. The process development requires the systematic investigation of several etching chemistries and plasma operating conditions for each metal investigated, namely TiN and TaN. In particular, it is necessary to find a plasma chemistry leading to the formation of volatile etch products from the metal layer (to prevent their redeposition on the gate sidewalls, which leads to a tapered profile and CD gain). Another important point is to control precisely the thickness of the passivation layer on the silicon sidewalls during the p-Si etching step. This layer is mandatory to prevent undercutting of the silicon sidewalls (in particular during the metal etching step), but if it becomes too thick sloped sidewalls are generated. To address this issue, XPS analysis of the gate sidewalls passivation layer is performed both after silicon etching and after the full stack patterning. It will be shown that XPS analysis, coupled to SEM and TEM, is a key technique that allows the development of plasma operating conditions that leads to an anisotropic etching profile of the poly-Si/metal gate stack. The other challenge associated with the introduction of the thin metal layer in the gate stack is to obtain a high etching selectivity toward ultra-thin SiON or high-k gate dielectric (HfSiOx and HfO₂). As often in plasma etching processes, profile control (anisotropy) and selectivity cannot be achieved under the same plasma conditions. We have investigated the metal/gate dielectric etching selectivities. In this study, AFM measurements coupled- to XPS analyses are used to characterize the impact of the gate etch process on the gate dielectric, allowing the development of selective processes free of metallic residues on the dielectric surface. Finally, the dry etch of hafnium based dielectric, when present in the gate stack, is addressed. This very thin (3.5 nm typ.) layer needs to be etched without any induced damage either in the active area (zero Si recess budget) or in the p-Si/metal gate profile previously patterned