Low-complexity Two Instruction Set Computer architecture for sensor network using Skipjack encryption

This paper presents a low-complexity hardware design and implementation of the Skipjack algorithm using the Two Instruction Set Computer (TISC) on a Xilinx Spartan-3 FPGA. The proposed low-complexity design makes use of the TISC processor architecture with only Adder and XOR hardware ALU blocks to perform the complete Skipjack encryption onto plaintext data. The hardware architecture was verified using the Handel-C hardware description language uses only a single memory block RAM and only 129 instructions for a complete 32 rounds of encryption. The TISC Skipjack processor occupies only 1% of the Spartan-3 available chip area, which are 116 occupied slices in total, making it a suitable choice for implementation in sensor networks for embedded security where hardware resources are scarce.