Transistor permutation for better transistor chaining

Custom layout design style remains to be an effective way of improving and differentiating the performance of integrated circuits. In this paper, we revisit the classic problem of transistor chaining, a key step in transistor level layout generation and report a systematic method for permutating transistors in a circuit topology such that without altering its logic function, the chance of finding transistor chains with minimum number of diffusion breaks is increased. The results on nontrivial circuits show that our algorithm can consistently outperform the best reported results in the literature.