Fast timing recovery for linearly and nonlinearly modulated systems

Digital phase-lock loop (PLL) is often used for timing recovery. Some nondata-aided timing error detectors occasionally cause hangup problem in the digital PLL. In this paper we introduce a new two-step antihangup timing recovery scheme. By simulations, we show that this enhanced scheme greatly reduces the probability of hangup and speeds up timing recovery for both linearly and nonlinearly modulated systems.