Title :
1-M sample/sec 12-bit low-power pipelined A/D converter
Author :
Valencic, Vlado ; Anghinolfi, Francis ; Deval, Philippe ; Krummenacher, François ; Jarron, Pierre ; Heijne, Erik H.M. ; Declercq, Michel
Author_Institution :
Mead Microelectron. SA, Crissier, Switzerland
Abstract :
A 12-b switched-capacitor (SC) pipelined A/D converter has been developed in the framework of the CERN LAA project for particle physics detector R&D. The integral linearity of the converter is improved by an autocalibration cycle compensating the ratio error between two nominally identical capacitors. The circuit has been manufactured using a low-voltage 3-μm CMOS technology. The active chip area including registers and clocking circuitry is 5.25 mm2. Experimental results indicate 11-b resolution for 1-MHz sampling frequency, with only 6-mW power consumption
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; error compensation; error correction; pipeline processing; switched capacitor networks; 1 MHz; 3 micron; 6 mW; CMOS technology; autocalibration cycle; charge injection compensation; gain error correction; low-power; low-voltage; pipelined A/D converter; ratio error compensation; switched-capacitor; CMOS technology; Capacitors; Circuits; Clocks; Detectors; Linearity; Manufacturing; Registers; Sampling methods; Switching converters;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112384
