On synthesizing application-specific array architectures from behavioral specifications

The authors describe a design framework, Architect, being developed for synthesizing application-specific array architectures from behavioral specifications to Register-Transfer (RT) descriptions , which can be identified as a number of cooperating tasks; signal transformations, hardware mapping expressed as, in general, nonlinear mapping and scheduling function with hardware constraints, memory management and controller synthesis. The authors present novel extensions to existing formal (i.e., ILP) and heuristics methods for multiplexing and clustering allowing constrained hardware allocation. Also a novel approach for optimizing on-chip memory is presented