Research and implementation of speaker recognition algorithm based on FPGA

As one of biometric identification technologies, speaker recognition shows better application prospects in many fields. At present, the implementation of speaker recognition algorithm on the hardware is mostly based on System on a Programmable Chip(SOPC) platform of Field Programmable Gate Array(FPGA) with Nios II Intellectual Property(IP) core. And the algorithm can be selected and optimized effectively on SOPC. However the high-speed and parallel operation of FPGA can´t be fully utilized. By researching and analyzing the speaker recognition algorithm, a FPGA-based speaker recognition method is presented in this paper. This method includes the Voice Active Detection (VAD), Mel Frequency Cepstrum Coefficient (MFCC) extraction and Vector Quantization (VQ) recognition algorithm. By using the technology such as Ping-pang operation, Pipeline and module reuse, it makes full use of FPGA´s speed. After testing, this method can effectively meet the requirement of real-time data processing.