Efficient floor-planning methodology for the Jasper Forest SoC on a 45 nanometer process

Floor-planning is usually one of design bottleneck for physical design convergence. For a complex SoC such as Jasper Forest, being concurrently developed and integrated with a leading edge CPU (Nehalem), floor-planning becomes even a bigger challenge to convergence on a very tight schedule. This paper highlights the floor-plan methodology and implementation details for Jasper Forest, with 782 million transistors, optimized for a 45 nm process. The methodology features an abutment LEGO structure floor-plan partitioning, a hybrid look-ahead floor-planning methodology, a semi-custom global clock tree construction, and Correct-by-Construction practices. These unique and innovative floor-planning methods enabled us to appropriately decouple complex design processes, minimize design dependencies, avoid non value added steps, and reduce the number of iterations to achieve the business goal of fast turnaround time with fewer resources.