A DVB-S2 compliant LDPC decoder integrating the Horizontal Shuffle Scheduling

Low-density parity check codes (LDPC) are a class of channel decoding codes used in digital communications. Very high error correcting performances can be reached with such codes but they require both a great computing effort and randomly constructed decoding matrices. LDPC codes are used to perform the channel coding of the satellite television broadcast standard DVB-S2. This paper proposes a way to design massively parallel hardware architecture of DVB-S2 compliant LDPC decoders. It is based on a particular way to schedule all the algorithm´s calculations. The proposed architecture speeds-up the decoding process, allowing the algorithm to converge faster with no significant performance loss. Moreover, a particular data update mechanism has been developed in order to avoid all data conflicts inherent to DVB-S2 matrices even for highly parallel implementations. This paper describes our hardware LDPC decoder architecture and its processing elements. Estimated silicon area of this decoder is 11 mm in ST 90 nm technology and the decoding throughput reaches 591 M bps at 300 MHz for rate 1/2 and code size of 64800