A study and design of CMOS H-Tree clock distribution network in system-on-chip

Author

Loo, Wei Khee ; Tan, Kok Siang ; Teh, Ying Khai

Author_Institution

Fac. of Eng., Multimedia Univ., Cyberjaya, Malaysia

fYear

2009

fDate

20-23 Oct. 2009

Firstpage

411

Lastpage

414

Abstract

A design of a low skew clock distribution network is presented based on the TSMC 0.18 Â¿m CMOS technology. This work first investigated various aspects in designing a clock distribution network. After that, the design methodology for the chosen H-Tree clock network topology is presented. A series of design performance analyses such as clock delay, skew, rise and fall time, supply voltage and temperature variations and power consumption were compared for both pre-layout and post-layout simulation results. Pre-layout and post-layout simulation results validated the 3-segment Â¿-model. The clock network designed is able to operate up to maximum clock speed of 1.1 GHz for a 1Ã—1 mm² chip with zero skew.

Keywords

CMOS integrated circuits; clocks; integrated circuit design; network topology; system-on-chip; CMOS H-Tree clock distribution network; H-Tree clock network topology; clock delay; design methodology; design performance analysis; low skew clock distribution network; power consumption; size 0.18 mum; supply voltage; system-on-chip; temperature variation; CMOS technology; Clocks; Delay effects; Design methodology; Energy consumption; Network topology; Performance analysis; System-on-a-chip; Temperature; Voltage; CMOS digital integrated circuits; Clocks;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Conference_Location

Changsha, Hunan

Print_ISBN

978-1-4244-3868-6

Electronic_ISBN

978-1-4244-3870-9

Type

conf

DOI

10.1109/ASICON.2009.5351254

Filename

5351254