Realization of a real time phasecorrelation chipset used in a hierarchical two step HDTV motion vector estimator

The phasecorrelation algorithm - as a method for motion estimation - is a key component of todays TV and tomorrows HDTV-systems. One advantage of hardware realization of this algorithm for efficient real time processing - in opposite to blockmatching - is the possibility to process multiple pixels per system clock cycle. A suitable partition using three different VLSI-circuits to perform the phasecorrelation algorithm is going to be proposed. The system is able to handle block sizes from 32 × 16 up to 128 × 128, thus estimation of motion vectors limited to (-64..+64) pixel becomes possible. The estimated motion vectors are prepared by the phasecorrelation to be handled by a following blockmatching unit and are helpful to reduce hardware effort by limiting its search range. The combination of both algorithms leads to a two-step hierarchical motion estimator. To minimize the physical volume all external components except RAMs, have been integrated on three specialized chips, where all parameters are free programmable and no glue logic is required