Asynchronous relaxation of locally-coupled automata networks, with application to parallel VLSI implementation of iterative image processing algorithms

Array processors tailored to mesh-based iterative algorithms benefit from shifting to an asynchronous mode. An architecture implementing this functionally asynchronous state-space update with self-timed elementary processors can dispense with the overhead of classical data exchange protocols and offer a flexible hierarchical mapping of the state lattice onto the array. The performance and practical feasibility of this approach are assessed on two application examples: iterative elliptic PDE resolution and image motion estimation using mean field annealing based on Markov random fields models