The design of a sub-nanojoule asynchronous 8051 with interface to external commercial memory

In this paper, we present the design of an asynchronous 8051 microcontroller with interface to external commercial memory. The design consists of an asynchronous core implemented using dual-rail four-phase protocol, a 128 byte internal asynchronous RAM and other synchronous peripherals including interrupts, timers and serial port. The asynchronous core contains all standard 8051 instructions except for multiplication and division. The interface to external commercial ROM and SRAM is controlled by two internal counters with adjustable overflow values to accommodate potentially variable clock source and external memory access time. An acknowledge signal is generated once the counter overflows which indicates the completion of a read/write operation. The chip is implemented using Austria Micro Systems (AMS) 0.35¿m technology. It is able to operate at 0.22 MIPS and consume 141pJ/Instruction at 1.0V supply. Another two-stage pipelined version designed later operates at 0.3MIPS and consumes 180pJ/Instruction at the same supply.