DocumentCode
2649151
Title
Low-Complexity Real-Time LDPC Encoder Design for CMMB
Author
Peng Wang ; Yong-en Chen
Author_Institution
Commun. Software & ASIC Design Center, Tongji Univ., Shanghai
fYear
2008
fDate
15-17 Aug. 2008
Firstpage
1209
Lastpage
1212
Abstract
Based on modified LU decomposition theory with pivoting of sparse matrix, a low-complexity real-time LDPC encoder for CMMB was presented, which can support 2 different code rate (1/2 and 3/4). Multi- staged pipeline and Pingpong buffer architectures were used to improve throughput. An efficient memory organization for storing sparse matrices was also presented. Whole design was synthesized and routed on Altera Stratix II EP2S90. Highest frequency achieved over 200 MHz, with pure encoding rate 32.44 Mbps (1/2 code rate) and 67.16 Mbps (3/4 code rate). Beside, fully-parameterized LDPC encoder can support arbitrary H matrix LDPC code with only necessary initialized data of memory blocks.
Keywords
buffer storage; integrated memory circuits; matrix decomposition; parity check codes; sparse matrices; Altera Stratix II EP2S90; CMMB; H matrix LDPC code; LU decomposition theory; Pingpong buffer architectures; channel message memory blocks; fully-parameterized LDPC encoder; low-complexity real-time LDPC encoder design; memory blocks; memory organization; multistaged pipeline; sparse matrices; sparse matrix; Application specific integrated circuits; Error correction codes; Frequency; Hardware; Matrix decomposition; Parity check codes; Quantum cascade lasers; Signal design; Signal processing; Sparse matrices; CMMB standard; LDPC encoding; LU decomposition; Pingpong buffer; Pipeline design;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent Information Hiding and Multimedia Signal Processing, 2008. IIHMSP '08 International Conference on
Conference_Location
Harbin
Print_ISBN
978-0-7695-3278-3
Type
conf
DOI
10.1109/IIH-MSP.2008.15
Filename
4604260
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