• DocumentCode
    2649320
  • Title

    A period-processor-time-minimal schedule for cubical mesh algorithms

  • Author

    Scheiman, Chris ; Cappello, Peter

  • Author_Institution
    Dept. of Comput. Sci., California Univ., Santa Barbara, CA, USA
  • fYear
    1993
  • fDate
    25-27 Oct 1993
  • Firstpage
    261
  • Lastpage
    272
  • Abstract
    The paper, using a direct acyclic graph (dag) model of algorithms, investigates precedence constrained multiprocessor schedules for the n × n × n directed mesh. This cubical mesh is fundamental, representing the standard algorithm for square matrix product, as well as many other algorithms. Its completion requires at least 3n - 2 multiprocessor steps. Time-minimal multiprocessor schedules that use as few processors as possible are called processor-time-minimal. For the cubical mesh, such a schedule requires at least [3n2/4] processors. Among such schedules, one with the minimum period (i.e., maximum throughput) is referred to as a period-processor-time-minimal schedule. The period of any processor-time-minimal schedule for the cubical mesh is at least 3n/2 steps. This lower bound is shown to be exact by by constructing, for n a multiple of 6, a period-processor-time-minimal multiprocessor schedule that can be realized on a systolic array whose topology is a toroidally-connected n/2 × n/2 × 3 mesh
  • Keywords
    directed graphs; matrix multiplication; multiprocessing systems; parallel algorithms; processor scheduling; systolic arrays; cubical mesh algorithms; direct acyclic graph; maximum throughput; minimum period; multiprocessor steps; period-processor-time-minimal schedule; precedence constrained multiprocessor schedules; square matrix product; systolic array; toroidally-connected mesh; Boolean functions; Computational complexity; Computational modeling; Computer science; Concrete; Processor scheduling; Scheduling algorithm; Systolic arrays; Throughput; Topology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application-Specific Array Processors, 1993. Proceedings., International Conference on
  • Conference_Location
    Venice
  • ISSN
    1063-6862
  • Print_ISBN
    0-8186-3492-8
  • Type

    conf

  • DOI
    10.1109/ASAP.1993.397150
  • Filename
    397150