A proposal for a capture method of low power design intent

The logic designer examines a sequence of the power gate as specifications, and is decided. The logic designer should take responsibility. But big a factors in UPF and CPF is decided by a reason of the chip construction, as if divide it at the time of the insertion of the isolation cells, the insertion of the always on buffer, and the power switch capacity with placement location. These are not responsibility by the logic designers. The UPF and CPF require to the logic designer to define these in as the specifications. Then what will the specifications of the power supply interception that designer should define be originally? I make the thing which should examine the specifications about the power supply interception that I can select as each process by the process of the design as linkage, design intent clear and want to suggest a proposal for the future EDA tool.