DocumentCode
2649430
Title
A new multiport memory for high performance parallel processor system with shared memory
Author
Hirano, K. ; Ono, T. ; Kurino, H. ; Koyanagi, M.
Author_Institution
Graduate Sch. of Eng., Tohoku Univ., Sendai, Japan
fYear
1998
fDate
10-13 Feb 1998
Firstpage
333
Lastpage
334
Abstract
We describe a new multiport memory which is called Shared DRAM (SHDRAM) to solve bus-bottle neck problem in parallel processor system with shared memory. This SHDRAM has four ports. Therefore four processors can be directly connected to this memory without bus-bottle neck. The basic operation of SHDRAM is confirmed by computer simulation and measurement results
Keywords
digital simulation; parallel processing; performance evaluation; shared memory systems; bus-bottle neck problem; computer simulation; high performance parallel processor system; measurement results; multiport memory; shared memory; Automatic logic units; Broadcasting; Cache memory; Concurrent computing; Intelligent systems; Machine intelligence; Neck; Parallel processing; Random access memory; Systems engineering and theory;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific
Conference_Location
Yokohama
Print_ISBN
0-7803-4425-1
Type
conf
DOI
10.1109/ASPDAC.1998.669491
Filename
669491
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