Title :
Multi-gate-length versus dual-gate-length biasing for active mode leakage power reduction: Benchmarking and modeling
Author :
Chen, Qiang ; Tirumala, Sridhar
Author_Institution :
Synopsys, Mountain View, CA, USA
Abstract :
Multi-gate-length (MGL) and dual-gate-length (DGL) biasing techniques are investigated for timing constraint-aware active mode leakage power reduction of VLSI circuits. Key design and technology characteristics essential for leakage reduction are identified and utilized to carry out a Monte-Carlo-based study to benchmark MGL against DGL over different design styles and various technologies. Extensive results indicate that MGL offers generally modest to small advantage over DGL. Novel analytical models have been developed to describe leakage reduction capability of DGL/MGL and reveal its dependences on key design/technology characteristics to quantitatively assess the cost-benefit trade-off of implementing DGL/MGL.
Keywords :
Monte Carlo methods; VLSI; integrated circuit design; integrated circuit modelling; integrated circuit testing; Monte Carlo methods; VLSI circuits; active mode leakage power reduction; dual-gate-length biasing; integrated circuit design; leakage reduction; multi-gate-length biasing; Analytical models; Circuit testing; Delay; Design optimization; Emulation; Logic design; Optimization methods; Runtime; Timing; Very large scale integration; Dual-gate-length; Leakage; Modeling; Monte-Carlo; Multi-gate-length; Optimization;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351283
