Implementation of large neural associative memories by massively parallel array processors

The authors discuss the use of massively parallel array processors for simulating large neural associative memories. Although based on standard matrix operations the simulation of neural associative memories requires special parallel algorithms because a sparse coding of the input and output information is needed. Four different implementations with different mapping strategies and different array processor topologies are presented and illustrated by example. The theoretical performance of all implementations is compared and the architecture of the massively parallel array processor PAN IV, designed for the efficient simulation for large neural associative memories is shortly described