A neural network processor incorporating multiple on-chip cache memories

The authors propose a virtually implemented neural network processor which is suitable for VLSI implementation. Three separate directly mapped on-chip caches are used to form a pipeline structure in the processor design. This architecture provides the base upon which evaluation of an appropriate cache write policy in the neurocomputing environment is possible. The need for instructions in the processor is eliminated by providing only two key words for the user. The processor is examined with reference to an existing conventional reduced instruction set computer (RISC) and it was estimated that when the processor with a total of just over 20 kbytes of on-chip cache is integrated on a single chip, it will compute the single dynamic loop of a neural network six times faster than the conventional RISC