BIST for ring-address SRAM-type FIFOs

Author

De Goor, Ad J. ; Schanstra, Ivo ; Zorian, Yervant

Author_Institution

Delft Univ. of Technol., Netherlands

fYear

1994

fDate

8-9 Aug 1994

Firstpage

112

Lastpage

118

Abstract

Testing FIFOs involves testing the embedded memory cell array, the addressing mechanisms, and the FIFO functionality logic (such as Empty and Full flags); each with their specific fault models. A test algorithm for the popular ring-address SRAM-type FIFOs has been published [Go94]; it consists of 36 steps and has a test length of 2n²+10n+12+2·Del (where n is the number of cells in the FIFO, and Del a delay time), while not all coupling faults are detectable due to the addressing restrictions of the FIFO. This paper presents a new test algorithm based on BIST which consists of 25 steps, reduces the test length to 21n+13+2·Del, and allows for full fault coverage. It has been implemented as part of a macro-cell generator for FIFOs at AT&T Microelectronics. The paper describes the test algorithm, the BIST hardware, and the chip area overhead

Keywords

SRAM chips; built-in self test; design for testability; fault diagnosis; integrated circuit testing; BIST; DFT; SRAM-type FIFO; chip area overhead; embedded memory cell array; fault models; full fault coverage; macro-cell generator; ring-address; test algorithm; Added delay; Built-in self-test; Circuit faults; Circuit testing; Decoding; Delay effects; Hardware; Logic arrays; Logic testing; Shift registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, 1994., Records of the IEEE International Workshop on

Conference_Location

San Jose, CA

Print_ISBN

0-8186-6245-X

Type

conf

DOI

10.1109/MTDT.1994.397188

Filename

397188