Title :
Fast FPGA placement algorithm using Quantum Genetic Algorithm with Simulated Annealing
Author :
Guo, Xiao ; Teng Wang ; Chen, Zhihui ; Wang, Lingli ; Zhao, Wenqing
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
Field-programmable gate array (FPGA) attracts more and more attentions in the digital-design field for its excellent features such as reconfiguration and fast time to market. But the implementation of FPGA is restricted by its hardware framework and the CAD software. This paper proposes quantum genetic algorithm with simulated annealing (QGASA) as a hybrid FPGA placement algorithm, which combined the advantage of the fast global search ability of QGA and local adjusting ability of simulated annealing (SA) algorithm. The experimental results are compared with the state-of-the-art placement tool versatile place and route (VPR) by running the MCNC benchmark circuits. The results show that the path-timing driven cost of QGASA is similar to VPR, but the overall CPU time is reduced by 70%.
Keywords :
benchmark testing; field programmable gate arrays; genetic algorithms; network analysis; simulated annealing; CAD software; CPU time; MCNC benchmark circuits; digital-design field; fast FPGA placement algorithm; fast global search ability; field-programmable gate array; hardware framework; quantum genetic algorithm; simulated annealing; versatile place-and-route tool; Central Processing Unit; Circuit simulation; Design automation; Field programmable gate arrays; Genetic algorithms; Logic circuits; Partitioning algorithms; Quantum computing; Simulated annealing; Wiring; FPGA placement; QGASA; congestion-avoidance; path-timing driven;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351309