Thermal via planning aware force-directed floorplanning for D ICs

The three-dimensional (3D) integration circuit is a new technology with higher integration density and better performance than 2D ICs. To solve the critical thermal issue in 3D layout, we propose a force-directed floorplanning algorithm. This algorithm naturally integrates with the planning of thermal vias and reasonably allocates white space for inserting the thermal vias. It solves the problem of the thermal distribution disturbance by the white space reassignment. Compare with the after-floorplanning thermal via planning algorithm, this algorithm decreases the number of thermal vias by 8.2% while increases the area by 3.5% on average.