GOS defects in SRAM: fault modeling and testing possibilities

A detailed analysis of the behavior of CMOS SRAM memories with gate oxide short defects is presented. Simulation results are obtained using a previously developed circuit model of the defect experimentally validated. Depending on the transistor affected by a gate oxide short, different SRAM faulty behaviors, as coupling faults or dynamic faults, can occur. Merits of logic and current testing are considered, comparing the fault coverage and test cost of each methodology. Results show that current testing gives a higher fault coverage with a lower cost. Finally a modified SRAM architecture is proposed to enhance testability for current testable defects. Such architecture allows the detection of any gate oxide short defect using only two test vectors