DocumentCode
2650066
Title
Random testability of redundant circuits
Author
Krasniewski, Andrzej ; Albicki, Alexander
Author_Institution
Dept. of Electr. Eng., Rochester Univ., NY, USA
fYear
1991
fDate
14-16 Oct 1991
Firstpage
424
Lastpage
427
Abstract
It is shown that the common belief that any optimized, i.e., nonredundant, circuit is easier to test than its nonoptimized counterpart is not fully justified. It is demonstrated by example that a redundant circuit may be more suitable for random testing than its optimized counterpart. A rule which specifies when redundancy is likely to enhance random testability of a two-level AND-OR gate network is formulated
Keywords
integrated circuit testing; integrated logic circuits; logic testing; redundancy; random testing; redundancy; redundant circuits; two-level AND-OR gate network; Circuit faults; Circuit testing; Combinational circuits; Logic circuits; Logic gates; Logic testing; Minimization; Redundancy; Sequential analysis; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-2270-9
Type
conf
DOI
10.1109/ICCD.1991.139936
Filename
139936
Link To Document