Fully-parallel multi-megabit integrated CAM/RAM design

Author

Schultz, Kenneth J. ; Gulak, P. Glenn

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

fYear

1994

fDate

8-9 Aug 1994

Firstpage

46

Lastpage

51

Abstract

Previous implementations of large-capacity Content Addressable Memories (CAMs) have employed advanced fabrication techniques or serialized operation. This paper describes a more generally applicable fully-parallel solution based on circuit and architectural innovation. A “pre-classified” CAM is integrated into the same array as its target RAM, and both use the same core cells. Architecture and operation are described, as are two critical-path circuits: the match-line pull-down and the multiple match resolver. An 8 kb test chip is described, and simulation results for a 1 Mb configuration are presented

Keywords

cellular arrays; content-addressable storage; integrated circuit testing; integrated memory circuits; memory architecture; random-access storage; 8 Kbit; core cells; critical-path circuits; fully-parallel solution; integrated CAM/RAM design; match-line pull-down; memory architecture; multiple match resolver; pre-classified CAM; target RAM; Associative memory; CADCAM; Circuit simulation; Circuit testing; Computer aided manufacturing; Fabrication; History; Random access memory; Read-write memory; Technological innovation;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, 1994., Records of the IEEE International Workshop on

Conference_Location

San Jose, CA

Print_ISBN

0-8186-6245-X

Type

conf

DOI

10.1109/MTDT.1994.397198

Filename

397198