A high speed embedded cache design with non-intrusive BIST

Author

Kornachuk, Steve ; McNaughton, Larry ; Gibbins, Robert ; Nadeau-Dostie, Benoit

Author_Institution

Northern Telecom Electron. Ltd., Ottawa, Ont., Canada

fYear

1994

fDate

8-9 Aug 1994

Firstpage

40

Lastpage

45

Abstract

This paper describes a 155 MHz wide-word cache design and its test integration features. Design techniques for high speed CAM with single ended match line sensing and highly integrated RAM are described. A new cache BIST algorithm based on the SMARCH algorithm is presented. New techniques are described for the insertion of cache BIST access points into a high speed data path without compromising mission mode performance. Performance results of cache memory used for telecommunications microprocessor applications with 1 Kb of CAM referencing a 5 Kb RAM are presented

Keywords

SRAM chips; built-in self test; cache storage; content-addressable storage; integrated memory circuits; 1 Kbit; 155 MHz; 5 Kbit; SMARCH algorithm; access points; embedded cache design; high speed CAM; high speed data path; match line sensing; mission mode performance; nonintrusive BIST; telecommunications microprocessor applications; test integration features; wide-word cache; Built-in self-test; CADCAM; Circuit testing; Clocks; Computer aided manufacturing; Driver circuits; Impedance matching; Prefetching; Random access memory; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, 1994., Records of the IEEE International Workshop on

Conference_Location

San Jose, CA

Print_ISBN

0-8186-6245-X

Type

conf

DOI

10.1109/MTDT.1994.397199

Filename

397199