A scan chains combined-balance strategy for hierarchical SoC DFT

Intellectual property (IP) cores reused technology improves system-on-a-chip (SoC) design productivity. However, with more IP cores embedded in the deeper levels, the hierarchical architecture of SoC becomes complex, which also makes the test difficult. A scan chains combined-balance (SCCB) strategy is proposed in this paper to reconfigure and balance the scan chains, which helps reduce test time and overhead. The SCCB strategy is different from the traditional test method, wherein the test access mechanism (TAM) and Scheduling are established as a virtual flattened form. We take experiments to verify the SCCB strategy based on the ITC´02 benchmarks. The experimental results show that the SCCB strategy is effective.