Prospects for variation tolerant SRAM circuit designs

This paper discusses on prospects for area-scaling capabilities of many kinds of SRAM margin assist solutions for V_T variability issue, which are based on various efforts by not only the cell topology changes from 6 T to 8 T and 10 T but also incorporating of multiple cell terminal biasing and timing sequence controls of read and write. The various SRAM solutions are analyzed in light of an impact on the required area overhead for each design solution given by ever increasing V_T-random variation (¿_VT), resulting in a slowdown in the SRAM scaling pace. It has been shown that 6 T SRAM cell will be allowed a long reign even in 15 nm process node if ¿_VT can be suppressed to <70 mV thanks to EOT (Effective Oxide Thickness) scaling for LSTP (Low Standby Power) process, otherwise 10 T and 8 T with read modify write (RMW) will be needed after ¿_VT becomes >85 mV and 75 mV, respectively.