Title :
A 90-nm CMOS embedded low power SRAM compiler
Author :
Zhang, Zhao Yong ; Chen, Chia Cheng ; Zheng, Jian Bin
Author_Institution :
Memory Design Dept., AiceStar Technol. Corp., Suzhou, China
Abstract :
In this paper a highly flexible low power single port Static Random Access Memory (SRAM) compiler design is presented. The Divided Word Line (DWL) and Divided Bit Line (DBL) scheme were implemented for reducing active power. Particular emphasis was put to decrease standby power consumption in word line driver. The forced-stack devices as pulse generation element was introduced for sensing enable. This guarantees SRAM can work in low voltage without losing design margin. A test-chip with 17 embedded SRAMs has been fabricated in UMC 90-nm low leakage CMOS logic process.
Keywords :
CMOS memory circuits; SRAM chips; circuit layout CAD; integrated circuit design; low-power electronics; CMOS embedded SRAM compiler; CMOS low power SRAM compiler; divided bit line; divided word line; forced-stack devices; low leakage CMOS logic process; low power single port static random access memory; power consumption; pulse generation element; size 90 nm; word line driver; CMOS logic circuits; CMOS process; Circuit synthesis; Circuit testing; Driver circuits; Logic arrays; Logic testing; Pulse generation; Random access memory; Voltage; Low power; SRAM compiler; divided bit line; divided word line; forced-stack device; part power-gating; replica technique; self-timing;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351323
