DocumentCode
2650207
Title
A self-diagnostic BIST memory design scheme
Author
Tsung MO, Chin ; Len Lee, Chung ; Ching Wu, Wen
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
1994
fDate
8-9 Aug 1994
Firstpage
7
Lastpage
9
Abstract
This paper proposes a BIST structure for embedded RAMs. The structure has the self-diagnostic capability with only a minimal overhead. It degrades a little on the speed performance of the embedded RAM. Two sets of test patterns, MARCH and CHECKERBOARD, which detect most of the memory faults, are adopted in the scheme. This self-diagnosis capability makes this RAM BIST scheme able to be incorporated for the embedded RAM self-repaired redundant design to increase its yield
Keywords
SRAM chips; built-in self test; cellular arrays; circuit optimisation; fault diagnosis; integrated circuit yield; random-access storage; redundancy; CHECKERBOARD; MARCH; embedded RAMs; memory faults; minimal overhead; self-diagnostic BIST; self-repaired redundant design; speed performance; test patterns; yield; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Counting circuits; Electrical fault detection; Fault detection; Random access memory; Read-write memory; Shift registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Technology, Design and Testing, 1994., Records of the IEEE International Workshop on
Conference_Location
San Jose, CA
Print_ISBN
0-8186-6245-X
Type
conf
DOI
10.1109/MTDT.1994.397205
Filename
397205
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