Title :
Characterization of WID delay variability using RO-array test structures
Author :
Onodera, Hidetoshi ; Terada, Haruhiko
Author_Institution :
Dept. of Commun. & Comput. Eng., Kyoto Univ., Kyoto, Japan
Abstract :
Characterization of delay variability on a real silicon is one of key challenges for DFM&Y. We have measured D2D and WID delay variability in 65 nm, 90 nm, and 180 nm processes using RO-array test structures, and decomposed WID variability into three components of random, deterministic, and systematic variation in descending order of magnitude for all three processes at a single-gate level.
Keywords :
CMOS integrated circuits; delays; integrated circuit design; oscillators; D2D delay variability; RO-array test structures; WID delay variability; die-to-die delay variability; ring oscillator; single-gate level; within-die delay variability; Adders; Circuit topology; Degradation; Delay effects; Multicore processing; Sleep; Switching circuits; Testing; Threshold voltage; Timing; D2D variation; RO-array; SSTA; WID variation; delay variability; test structure;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351332
