Title :
Logical effort of higher valency adders
Author_Institution :
Harvey Mudd Coll., Claremont, CA, USA
Abstract :
Higher valency parallel prefix adders reduce the number of logic levels at the expense of greater fan-in at each level. This paper uses the method of logical effort to evaluate the tradeoffs of higher valency for static and dynamic implementations of various adder architectures.
Keywords :
adders; logic gates; valency; adder architectures; higher valency adders logical effort; logic levels reduction; parallel prefix adders; Adders; Circuits; Computer architecture; Delay estimation; Educational institutions; Libraries; Logic; Microprocessors; Propagation delay; Wire;
Conference_Titel :
Signals, Systems and Computers, 2004. Conference Record of the Thirty-Eighth Asilomar Conference on
Print_ISBN :
0-7803-8622-1
DOI :
10.1109/ACSSC.2004.1399375
