Implementation of high-speed verification platform based on emulator for ReDSP and ReMAP

Author

Wei, Huang ; Xinan, Wang ; Peng, Dai ; Zheng, Guo

Author_Institution

Shenzhen Grad. Sch., Peking Univ., Shenzhen, China

fYear

2009

fDate

20-23 Oct. 2009

Firstpage

682

Lastpage

685

Abstract

Verification of processors with high performance is becoming more and more time-consuming and even gradually turning into the bottleneck of the processor design. The verification of reconfiguralbe multimedia array processor (ReMAP) we designed for multimedia processing and its internal component reconfigurable DSP(ReDSP) is also no exception. A high-speed verification platform based on emulator is proposed for ReDSP and ReMAP. We demonstrate the hardware architecture of the platform and different verification modes it supports. A software verification model is proposed, and the evaluation results show a great acceleration rate compared to software simulation.

Keywords

digital signal processing chips; logic design; program verification; digital signal processing chips; emulator; hardware architecture; high-speed verification platform; internal component reconfigurable DSP; multimedia processing; processor verification; reconfiguralbe multimedia array processor; software simulation; software verification model; Acceleration; Computer architecture; Electronic mail; Emulation; Field programmable gate arrays; Hardware; Logic testing; Microprocessors; Process design; Turning; emulator; software simulation; verification;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Conference_Location

Changsha, Hunan

Print_ISBN

978-1-4244-3868-6

Electronic_ISBN

978-1-4244-3870-9

Type

conf

DOI

10.1109/ASICON.2009.5351338

Filename

5351338