A self-testing assisted pipelined-ADC calibration technique

For embedded analog-to-digital converters (ADCs) fabricated with deep sub-micron technology, calibration has become mandatory to ensure acceptable yield against process variations. This paper presents a pipelined ADC calibration technique that targets the capacitor mismatch and comparator offset associated with the pipelined ADC stages. The calibration technique is self-testing assisted; it utilizes the built-in histogram testing circuitry to (1) obtain the necessary calibration information, and (2) validate the calibrated ADC. Simulation results show that the calibration strategy substantially enhances the ADC static linearity and dynamic performance.