DocumentCode :
2650618
Title :
Output test compression for compound defect diagnosis
Author :
Tzeng, Chao-Wen ; Huang, Shi-Yu
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu, Taiwan
fYear :
2009
fDate :
20-23 Oct. 2009
Firstpage :
569
Lastpage :
572
Abstract :
In modern scan architecture, it is often desired to compact the output response without jeopardizing the diagnostic resolution. In this work, we propose an output masking scheme to meet such a stringent requirement. We consider a practical scenario in which an output compactor is in use. We aim to support the harshest condition called compound defect diagnosis, in which faults exist in both the scan chain and the core logic. To overcome the loss of the diagnostic resolution, we incorporate a split-masking scheme, by which one can easily separate the output responses of the faulty chains from those of the fault-free ones. The experimental results demonstrate that the proposed scheme can recover the diagnostic resolution loss induced by an output compactor almost completely without sacrificing the compaction ratio.
Keywords :
comparators (circuits); fault diagnosis; logic circuits; logic testing; compound defect diagnosis; core logic; diagnostic resolution loss; output compactor; output test compression; scan chain; split-masking scheme; Chaos; Compaction; Continuous wavelet transforms; Contracts; Economic forecasting; Equations; Fault diagnosis; Flip-flops; Logic testing; Partitioning algorithms; Compound Defect Diagnosis; Output Masking Scheme; Scan Test; Test Compression;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
Type :
conf
DOI :
10.1109/ASICON.2009.5351349
Filename :
5351349
Link To Document :
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