Title :
A high performance IIR digital filter chip
Author :
Woods, R.F. ; McCanny, J.V. ; Knowles, S.C. ; McNally, C.
Author_Institution :
Dept. of Electr. Eng., Queens Univ. of Belfast, UK
Abstract :
The design of a high-performance IIR (infinite impulse response) digital filter is described. The chip architecture operates on 11-bit parallel, two´s complement input data with a 12-bit parallel two´s complement coefficient to produce a 14-bit two´s complement output. The chip is implemented in 1.5-μm, double-layer-metal CMOS technology, consumes 0.5 W, and can operate up to 15 Msample/s. The main component of the system is a fine-grained systolic array that internally is based on a signed binary number representation (SBNR). Issues addressed include testing, clock distribution, and circuitry for conversion between two´s complement and SBNR
Keywords :
CMOS integrated circuits; VLSI; digital filters; digital integrated circuits; 0.5 W; 1.5 micron; 11 to 15 bit; 15 MHz; CMOS; IIR digital filter chip; SBNR; chip architecture; circuitry for conversion; clock distribution; double-layer-metal; fine-grained systolic array; sampling rate; signed binary number representation; testing; two´s complement; CMOS technology; Chip scale packaging; Circuit testing; Clocks; Computer architecture; Digital filters; Hardware; IIR filters; Microelectronics; Systolic arrays;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112395
