DocumentCode
2650696
Title
F-scan: An approach to functional RTL scan for assignment decision diagrams
Author
Obien, Marie Engelene J ; Fujiwara, Hideo
Author_Institution
Comput. Design & Test Lab., Nara Inst. of Sci. & Technol., Kansai Science City, Japan
fYear
2009
fDate
20-23 Oct. 2009
Firstpage
589
Lastpage
592
Abstract
This paper presents a new methodology for functional register transfer level (RTL) scan, in which existing functional elements and paths can be maximally utilized. The approach is called F-scan, which primarily aims to reduce the total area overhead due to augmentation for testing. Since the method allows for parallel scanning of test vectors, test application time is also made to be at the minimum. The case study shows the effectiveness of our approach compared to full scan design.
Keywords
design for testability; logic testing; sequential circuits; F-scan; assignment decision diagrams; design-for-testability; functional RTL scan; functional register transfer level scan; parallel scanning; sequential circuits testability; test vectors; Circuit testing; Controllability; Design for testability; Flip-flops; Logic testing; Multiplexing; Observability; Registers; Sequential analysis; Sequential circuits; Scan design; assignment decision diagram; design-for-testability; functional RTL;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location
Changsha, Hunan
Print_ISBN
978-1-4244-3868-6
Electronic_ISBN
978-1-4244-3870-9
Type
conf
DOI
10.1109/ASICON.2009.5351354
Filename
5351354
Link To Document