Function-Level Processor (FLP): A High Performance, Minimal Bandwidth, Low Power Architecture for Market-Oriented MPSoCs

This letter introduces function-level processors (FLPs) to fill the flexibility/efficiency gap between instruction-level processors (ILPs) and hardware accelerators (HWACCs). Compared to an ILP, an FLP has a coarser programmability at function-level constructed out of configurable function blocks (FBs) implementing market-oriented functions. FBs are connected via a MUX-based programmable interconnect, tuned for envisioned application flows, for realizing flexible macro pipelines. We demonstrate FLP benefits with an industry example of the pipeline-vision processor (PVP). Mapping six embedded vision applications, the PVP offers up to 22.4 GOPs/s with average power of 120 mW; consuming 17x and 6x less power than compared ILP and ILP + HWACCs approaches.