Improved cellular structures for bit-steered ROM finite ring systolic arrays

A discussion is presented of radical improvements to a small steerable ROM structure that is used in linear bit-level systolic arrays for finite ring computations. The new circuit allows a single bit computation, on a fixed coefficient inner product step, to be computed by the evaluation of individually pipelined dynamic nodes. The absence of a chain of logic gates (static or dynamic) within the bit-level cell allows very fast operation of the pipeline; mask extracted SPICE simulations predict 50-MHz pipeline rates for 3-μm CMOS. A complete word-level inner product step is available with a maximum latency of only 10 pipeline clock cycles using 5-bit ring moduli